(1) Field of the Invention
The present invention relates to a semiconductor memory device having flip-flop circuits, and more particularly to a semiconductor memory device having flip-flop circuits in which an erroneous operation occurs due to a noise induced in the conductors connected to the input terminals of the flip-flop circuits.
(2) The Prior Art
An example of the prior art semiconductor memory device using MOS FETs is illustrated in FIG. 1. In FIG. 1, the semiconductor memory device comprises sense amplifiers 31, 32, . . . , 3N which read-out the information stored in memory elements and an input/output (I/O) amplifier 4. Each of the sense amplifiers 31, 32, . . . , 3N and the I/O amplifier 4 consists of a flip-flop circuit. Each of the sense amplifiers 31, 32, . . . , 3N is connected to a pair of bit lines 11, 21; 12, 22; . . . ; 1N, 2N, respectively. The I/O amplifier 4 is connected to a pair of data bus lines 51, 52.
When the sense amplifiers 31, 32, . . . , 3N amplify the signals on the bit lines 11, 21; 12, 22; . . . 1N, 2N in accordance with the read clock signal .phi.R, noise is induced in the data bus lines 51, 52 from the bit lines 11, 21; 12, 22; . . . 1N, 2N due to the existence of the coupling capacitances C.sub.1, C.sub.2, . . . C.sub.N. It is assumed that the information to be read-out exists in the pair of bit lines 11, 21 but not in the pairs of bit lines 12, 22 through 1N, 2N. The value of the noise .DELTA.VN.sub.2 induced in the data bus line 52 is represented by the equation (1) below. ##EQU1## Here, C.sub.m is the capacitance between the data bus line 52 and ground and .DELTA.V.sub.B2 is the variation of the voltage of bit line 22. The value of the noise .DELTA.VN.sub.1 induced in the data bus line 51 is approximately equal to zero EQU .DELTA.VN.sub.1 .apprxeq.0 (2)
The input voltage V.sub.S applied to the I/O amplifier 4 is represented by the equation (3) below. ##EQU2## Here, C.sub.B is the capacitace between the bit line and the ground and .DELTA.V.sub.B1 is the variation of the voltage of bit line 11.
In the case where the data of the cell to be read-out is the same as the data of the cells not to be read-out, the phase of the noise .DELTA.VN.sub.2 of the equation (1) is the same as the phase of the voltage V.sub.S of the equation (3), and, accordingly, no erroneous operation of the I/O amplifier 4 is caused. In contrast, in the case where the data of the cell to be read-out is the opposite of the data of the cells not to be read-out, the phase of the noise .DELTA.VN.sub.2 of the equation (1) is the reverse of the phase of the voltage V.sub.S of the equation (3), and, accordingly an erroneous operation of the I/O amplifier 4 is caused if the absolute value of the noise .DELTA.VN.sub.2 is greater than the absolute value of the voltage V.sub.S.
The above described operation of the circuit of FIG. 1 is illustrated by the wave forms I, II and III of FIG. 3.
At first, when the precharge clock signal .phi.p is applied to the gates of the FETs connected to the bit lines 11 and 21 the potentials (H, L) of the bit lines 11 and 21 start to change so as to be equalized and to attain a high level as shown in the wave form I. Then, when the signal Xm is applied to the gate of the FET connected to the real cell C.sub.R, the equalized potentials of the bit lines 11 and 21 become different. Then, when the read clock signal .phi.R is applied to the sense amplifier 31, the sense amplifier 31 starts to operate so that the potential difference between the bit lines 11 and 21 becomes greater. Thus, the potentials of the bit lines 11 and 21 are brought to the low level (L) and the high level (H), respectively, as shown in the wave form I.
It is assumed that the changes of the potentials of the bit lines 12, 22 through 1N, 2N from which no stored information is to be read-out are the reverse of the bit lines 11, 21 as shown in the wave form II.
The process of the change of the potentials of the data bus lines 51 and 52 due to the effect of the noise induced from the bit lines is illustrated in the wave form III. Due to the existence of the noise .DELTA.VN.sub.2 of equation (1), the potential of the data bus line 52 falls (F) as shown in the wave form III. Under these conditions, when the decoder signal Y.sub.1 is applied to the FETs connected between the bit lines 11, 21 and the data bus lines 51, 52 and the data clock signal .phi..sub.D is applied to the I/O amplifier 4, the potential of the data bus line 51 remains high and the potential of the data bus line 52 becomes low. This potential distribution between the data bus lines 51 and 52 reversely corresponds to the potential distribution between the bit lines 11 and 21 in the wave form I. Accordingly, the potential distribution between the data bus lines 51 and 52 provides erroneous operation due to the induced noise.
The prior art semiconductor memory devices having flip-flop circuits are disclosed in, for example, U.S. Pat. No. 3,514,765 and thesis "The Design of MOS Dynamic RAMs" by R.C. Foss, 1979 IEEE International Solid-state Circuits Conference.